A second-order VCO-based ∆Σ ADC using a modified DPLL

Introduction: Voltage-controlled oscillators (VCO) have drawn a lot of attention from data converter community recently [1–5]. A VCO acts as an integrator in phase domain and can form a basic building block in time-domain analog-to-digital converters (ADCs), similar to operational transconductance amplifiers (OTAs) in traditional voltage-domain ADCs. Due to the highly digital nature of VCOs, they are well suited for design in advanced technologies. In addition, VCO quantization noise depends on transistor delay and reduces with technology scaling, thus providing a strong incentive to use VCO-based time-domain ADCs in advanced technology nodes. However, unlike OTA-based ∆Σ ADCs, higher-order time-domain ∆Σ ADCs cannot be built by cascading multiple VCOs. This is because if multiple VCOs are cascaded, the overall quantization noise is dominated by the first stage and is only first-order shaped. Thus, VCOs have mostly been used to design first-order∆Σ ADCs and higherorder noise shaping has been achieved by using OTAs in conjunction with VCO. [4] has reported a purely VCO based second-order∆Σ ADC. A phase-locked loop (PLL) based ∆Σ ADC is reported in [5] which achieves second-order noise shaping using a passive loop filter. In this letter, we propose a novel architecture to achieve secondorder ∆Σ using VCOs without requiring OTAs or other complicated analog components. Compared to [4], the proposed architecture reduces the number of digital-to-analog converters (DACs). The proposed architecture requires a much smaller area than [5] as no passive loop filter is used. In addition, the ADC in [5] achieves second-order noise shaping between the pole and zero frequencies of the loop filter and not at low frequency. This is in contrast to the proposed architecture which shapes the entire in-band noise to second-order and thus has a lower in-band noise floor than [5]. The proposed technique can be extended to build higher-order (> 2) VCO-based ∆Σ ADCs.